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GS9090 参数 Datasheet PDF下载

GS9090图片预览
型号: GS9090
PDF下载: 下载PDF文件 查看货源
内容描述: GS9090 GenLINX -R III 270MB / s的解串器的SDI和DVB -ASI [GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI]
分类和应用:
文件页数/大小: 70 页 / 1181 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS9090 Data Sheet  
3.14.1 Command Word Description  
The command word consists of a 16-bit word transmitted MSB first and contains a  
read/write bit, an Auto-Increment bit and a 12-bit address. Figure 3-16 shows the  
command word format and bit configurations.  
Command words are clocked into the GS9090 on the rising edge of the serial clock  
SCLK, which operates in a burst fashion.  
When the Auto-Increment bit is set LOW, each command word must be followed  
by only one data word to ensure proper operation. If the Auto-Increment bit is set  
HIGH, the following data word will be written into the address specified in the  
command word, and subsequent data words will be written into incremental  
addresses from the previous data word. This facilitates multiple address writes  
without sending a command word for each data word.  
Auto-Increment may be used for both read and write access.  
3.14.2 Data Read and Write Timing  
Read and write mode timing for the GSPI interface is shown in Figure 3-18 and  
Figure 3-19 respectively. The timing parameters are defined in Table 3-21.  
When several devices are connected to the GSPI chain, only one CS must be  
asserted during a read sequence.  
During the write sequence, all command and following data words input at the  
SDIN pin are output at the SDOUT pin as is. Where several devices are connected  
to the GSPI chain, data can be written simultaneously to all the devices that have  
CS set LOW.  
Table 3-21: GSPI Timing Parameters  
Parameter  
Definition  
Specification  
t0  
The minimum duration of time chip select, CS, must be  
LOW before the first SCLK rising edge.  
1.5 ns  
t1  
t2  
t3  
t4  
The minimum SCLK period.  
Duty cycle tolerated by SCLK.  
Minimum input setup time.  
18.5 ns  
40% to 60%  
1.5 ns  
Write Cycle: the minimum duration of time between the  
last SCLK command (or data word if the Auto-Increment  
bit is HIGH) and the first SCLK of the data word.  
37.1 ns  
t5  
Read Cycle: the minimum duration of time between the  
last SCLK command (or data word if the Auto-Increment  
bit is HIGH) and the first SCLK of the data word.  
148.4 ns  
222.6 ns  
t5  
Read Cycle - FIFO in ANC Extraction Mode: the minimum  
duration of time between the last SCLK command (or data  
word if the Auto-Increment bit is HIGH) and the first SCLK  
of the data word.  
t6  
Minimum output hold time.  
1.5 ns  
28201 - 1 July 2005  
60 of 70  
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