GS9090 Data Sheet
3.15 Reset Operation
When the RESET signal on the GS9090 is de-asserted (RESET = LOW to HIGH)
the LOCKED and DATA[9:0] signals are valid after a period of 200ns after fhe rising
edge of the RESET signal. (See Figure 3-20)
The application layer should not sample the LOCKED or DATA[9:0] signals during
this time.
RESET
LOCKED
DOUT[9:0]
Invalid
Data
200ns
Figure 3-20: Reset Timing
3.16 JTAG Operation
When the JTAG/HOST pin is set HIGH by the application layer, the host interface
port (as described in GSPI Host Interface on page 59) will be configured for JTAG
test operation. In this mode, pins 16, 17, 19, and 20 become TMS, TCK, TDO, and
TDI respectively. In addition, the RESET pin will operate as the test reset pin, as
well as resetting the internal registers.
Boundary scan testing using the JTAG interface will be possible in this mode.
There are two methods in which JTAG can be used on the GS9090:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other
devices driving the digital I/O pins. If the tests are to be applied only at ATE, this
can be accomplished with tri-state buffers used in conjunction with the
JTAG/HOST input signal. This is shown in Figure 3-21.
Alternatively, if the test capabilities are to be used in the system, the host may still
control the JTAG/HOST input signal, but some means for tri-stating the host must
exist in order to use the interface at ATE. This is represented in Figure 3-22.
28201 - 1 July 2005
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