GS9090 Data Sheet
Table 3-19: STAT [3:0] Output Default Configuration (Continued)
Device Configuration
IO_CONFIG
Register
I/O
Function
Default IO_CONFIG
Setting
Data-Through
SMPTE_BYPASS = LOW
DVB_ASI = LOW
STAT0_CONFIG
STAT1_CONFIG
STAT2_CONFIG
STAT3_CONFIG
Output
Output
Output
Output
High Z
High Z
High Z
High Z
000b
000b
000b
000b
3.13 GS9090 Low-latency Mode
When the IOPROC_EN pin is set LOW, the GS9090 will enter a low-latency mode
such that the parallel data will be output with the minimum PCLK latency possible.
The FIFO and all processing blocks except the descrambling and word alignment
blocks will be bypassed when SMPTE_BYPASS is HIGH.
Low-latency mode will also be selected when SMPTE_BYPASS is set LOW,
regardless of the setting of the IOPROC_EN signal (see Table 3-20).
In DVB-ASI mode, the device will have a higher latency than low-latency mode,
although this latency will be less than SMPTE mode.
NOTE: When in low-latency mode, the STAT pin output of the ANC packet flag is
delayed by 15 PCLK cycles with respect to the parallel video output. The length of
the flag matches the length of the ANC packet.
Table 3-20: Pin Settings in Low-latency Mode
IOPROC_EN Setting
SMPTE_BYPASS
Setting
Latency (PCLK Cycles)
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
9
10
10
25
NOTE: Latency applies to parallel processing core only.
When the GS9090 is configured for low-latency mode, the H, V, and F output timing
will be TRS based blanking only as shown in Figure 3-14. Active line-based timing
is not available and the setting of the H_CONFIG host interface bit will be ignored.
28201 - 1 July 2005
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