GS9090 Data Sheet
3.14.3 Configuration and Status Registers
Table 3-22 summarizes the GS9090's internal status and configuration registers.
All of these registers are available to the host via the GSPI and are all individually
addressable.
Where status registers contain less than the full 16 bits of information, two or more
registers may be combined at a single logical address.
Table 3-22: GS9090 Internal Registers
Address
Register Name
Reference
00h
IOPROC_DISABLE
ERROR_STATUS
EDH_FLAG_IN
Error Correction and Insertion on page 43
Error Detection and Indication on page 38
EDH Flag Detection on page 33
01h
02h
03h
EDH_FLAG_OUT
DATA_FORMAT
EDH Flag Detection on page 33
04h
Video Standard Indication on page 38
Programmable Multi-Function Outputs on page 56
Reading From the FIFO on page 48
05h
IO_CONFIG
06h
FIFO_EMPTY_OFFSET
FIFO_FULL_OFFSET
ANC_TYPE
07h
Reading From the FIFO on page 48
08h - 0Eh
11h - 14h
Ancillary Data Detection and Indication on page 31
RASTER_STRUCTURE
Automatic Video Standard and Data Format
Detection on page 37
15h - 24h
25h
EDH_CALC_RANGES
ERROR_MASK
EDH CRC Error Detection on page 40
Error Detection and Indication on page 38
Programmable FIFO Load Position on page 30
Ancillary Data Extraction Mode on page 51
28h
FIFO_LD_POSITION
INTERNAL FIFO
02Ch - 42Bh
28201 - 1 July 2005
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