GS9060 Data Sheet
Table 3-14: Host Interface Description for EDH Flag Register
Register
Name
Bit
Name
Description
R/W
Default
EDH_FLAG
Address: 03h
15
14
13
12
11
10
9
Not Used
ANC-UES out
ANC-IDA out
ANC-IDH out
ANC-EDA out
ANC-EDH out
FF-UES out
FF-IDA out
Ancillary Unknown Error Status Flag.
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Ancillary Internal device error Detected Already Flag.
Ancillary Internal device error Detected Here Flag.
Ancillary Error Detected Already Flag.
Ancillary Error Detected Here Flag.
Full Field Unknown Error Status Flag.
8
Full Field Internal device error Detected Already Flag.
Full Field Internal device error Detected Here Flag.
Full Field Error Detected Already Flag.
7
FF-IDH out
FF-EDA out
FF-EDH out
AP-UES out
AP-IDA out
AP-IDH out
AP-EDA out
AP-EDH out
6
5
Full Field Error Detected Here Flag.
4
Active Picture Unknown Error Status Flag.
Active Picture Internal device error Detected Already Flag.
Active Picture Internal device error Detected Here Flag.
Active Picture Error Detected Already Flag.
Active Picture Error Detected Here Flag.
3
2
1
0
3.11 Parallel Data Outputs
Data outputs leave the device on the rising edge of PCLK as shown in Figure 3-7.
The data may be scrambled or unscrambled, framed or unframed, and may be
presented in 10-bit or 20-bit format. The output data bus width is controlled
independently from the internal data bus width by the 20bit/10bit input pin.
Likewise, the output data format is defined by the setting of the external
SMPTE_BYPASS and DVB_ASI pins. Recall that these pins are set by the
application layer as inputs to the device.
3.11.1 Parallel Data Bus Buffers
The parallel data outputs of the GS9060 are driven by high-impedance buffers
which support both LVTTL and LVCMOS levels. These buffers use a separate
power supply of +3.3V DC supplied via the IO_VDD and IO_GND pins.
All output buffers, including the PCLK output, may be driven to a high-impedance
state if the RESET_TRST signal is asserted LOW.
22208 - 8 January 2007
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