GS9060 Data Sheet
duty
cycle
period
t
2
t
4
t
0
t
5
SCLK
input data
setup time
t
3
CS
SDIN
output data
hold time
t
6
RSV
R/W
RSV
RSV
RSV RSV
RSV
RSV A5
A4
A3
A2
RSV
RSV
A1
A0
D9
D15 D14
D13
D12
D7
D5
D4
D2
D10
D8
D6
D3
D1
D0
D11
SDOUT
Figure 3-11: GSPI Read Mode Timing
duty
cycle
period
t
2
t
4
t
0
SCLK
input data
setup time
t
3
CS
RSV
R/W
RSV
RSV
RSV RSV
RSV
RSV A5
A4
A3
A2
D9
SDIN
RSV
A1
A0
D15 D14
D13
D12
D7
D5
D4
D2
RSV
D10
D8
D6
D3
D1
D0
D11
Figure 3-12: GSPI Write Mode Timing
3.12.3 Configuration and Status Registers
Table 3-16 summarizes the GS9060's internal status and configuration registers.
All of these registers are available to the host via the GSPI and are all individually
addressable.
Where status registers contain less than the full 16 bits of information however, two
or more registers may be combined at a single logical address.
Table 3-16: GS9060 internal registers
Address
Register Name
See Section
00h
IOPROC_DISABLE
ERROR_STATUS
EDH_FLAG
Section 3.10.6 on page 46
Section 3.10.5 on page 42
Section 3.10.7 on page 48
Section 3.10.4 on page 39
Section 3.10.2.1 on page 37
Section 3.10.3 on page 39
Section 3.10.4 on page 39
Section 3.10.5.2 on page 44
Section 3.10.5 on page 42
01h
03h
04h
VIDEO_STANDARD
ANC_TYPE
05h - 09h
0Ch - 0Dh
0Eh - 11h
12h - 19h
1Ah
VIDEO_FORMAT
RASTER_STRUCTURE
EDH_CALC_RANGES
ERROR_MASK
22208 - 8 January 2007
53 of 61
GENNUM [ GENNUM CORPORATION ]
