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GS9060-CF 参数 Datasheet PDF下载

GS9060-CF图片预览
型号: GS9060-CF
PDF下载: 下载PDF文件 查看货源
内容描述: HD - LINX II SD- SDI和DVB- ASI解串器,带环通电缆驱动器 [HD-LINX II SD-SDI and DVB-ASI Deserializer with Loop-Through Cable Driver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路
文件页数/大小: 61 页 / 885 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS9060 Data Sheet  
3.10.5.4 Ancillary Data Checksum Error Detection  
The GS9060 will calculate checksums for all received ancillary data and compare  
the calculated values to the received checksum words. If a mismatch is detected,  
the error is flagged in the CS_ERR bits of the ERROR_STATUS register.  
Although the GS9060 will calculate and compare checksum values for all ancillary  
data types by default, the host interface may program the device to check only  
certain types of ancillary data checksums.  
This is accomplished via the ANC_TYPE register as described in Section 3.10.2.1  
on page 37.  
3.10.5.5 TRS Error Detection  
TRS errors flags are generated by the GS9060 when:  
1. The received TRS timing does not correspond to the internal flywheel timing;  
or  
2. The received TRS hamming codes are incorrect.  
Both 8-bit and 10-bit SAV and EAV TRS words are checked for timing and data  
integrity errors. These are flagged via the SAV_ERR and/or EAV_ERR bits of the  
ERROR_STATUS register.  
Timing-based TRS errors will only be generated if the FW_EN/DIS pin is set HIGH.  
3.10.6 Error Correction and Insertion  
In addition to signal error detection and indication, the GS9060 may also correct  
certain types of errors by inserting corrected code words and checksums into the  
data stream. These features are only available in SMPTE mode and  
IOPROC_EN/DIS must be set HIGH. Individual correction features may be  
enabled or disabled via the IOPROC_DISABLE register (Table 3-13).  
All of the IOPROC_DISABLE register bits default to '0' after device reset, enabling  
all of the processing features. To disable any individual error correction feature, the  
host interface must set the corresponding bit HIGH in the IOPROC_DISABLE  
register.  
3.10.6.1 Illegal Code Remapping  
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the  
GS9060 will remap all codes within the active picture between the values of 3FCh  
and 3FFh to 3FBh. All codes within the active picture area between the values of  
000h and 003h will be re-mapped to 004h.  
In addition, 8-bit TRS and ancillary data preambles will be remapped to 10-bit  
values if this feature is enabled.  
22208 - 8 January 2007  
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