GS9060 Data Sheet
Table 3-13: Host Interface Description for Internal Processing Disable Register
Register Name
Bit
Name
Description
R/W
Default
IOPROC_DISABLE
Address: 00h
15-9
8
Not Used
H_CONFIG
Horizontal sync timing output configuration. Set LOW
for active line blanking timing. Set HIGH for H blanking
based on the H bit setting of the TRS words. See
Figure 3-3.
0
7
6
5
Not Used
Not Used
ILLEGAL_REMAP
Illegal Code re-mapping. Correction of illegal code
words within the active picture. Set HIGH to disable.
The IOPROC_EN/DIS pin must be set HIGH.
R/W
R/W
R/W
0
0
0
4
3
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error correction insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set HIGH.
ANC_CSUM_INS
Ancillary Data Check-sum insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set HIGH.
2-1
0
Not Used
TRS_INS
Timing Reference Signal Insertion. Set HIGH to disable.
The IOPROC_EN/DIS pin must be set HIGH.
R/W
0
3.10.6.2 EDH CRC Error Correction
The GS9060 will generate and insert active picture and full field CRC words into
the EDH data packets received by the device. This feature is only available in SD
mode and is enabled by setting the EDH_CRC_INS bit of the IOPROC_DISABLE
register LOW.
EDH CRC calculation ranges are described in Section 3.10.5.2 on page 44.
NOTE: Although the GS9060 will modify and insert EDH CRC words and EDH
packet checksums, EDH error flags will not be updated by the device.
3.10.6.3 Ancillary Data Checksum Error Correction
When ancillary data checksum error correction and insertion is enabled, the
GS9060 will generate and insert ancillary data checksums for all ancillary data
words by default. Where user specified ancillary data has been programmed into
the device Section 3.10.2.1 on page 37, only the checksums for the programmed
ancillary data types will be corrected.
This feature is enabled when the ANC_CSUM_INS bit of the IOPROC_DISABLE
register is set LOW.
22208 - 8 January 2007
47 of 61
GENNUM [ GENNUM CORPORATION ]
