GS9060 Data Sheet
3.9 Data Through Mode
The GS9060 may be configured by the application layer to operate as a simple
serial-to-parallel converter. In this mode, the device presents data to the output
data bus without performing any decoding, descrambling or word-alignment.
Data through mode is enabled only when the SMPTE_BYPASS and DVB_ASI
input pins are set LOW. Under these conditions, the lock detection algorithm enters
PLL lock mode, Section 3.6 on page 28, such that the device may reclock data not
conforming to SMPTE or DVB-ASI streams. The LOCKED pin will indicated analog
lock.
3.10 Additional Processing Functions
The GS9060 contains an additional data processing block which is available in
SMPTE mode only, Section 3.7 on page 30.
3.10.1 FIFO Load Pulse
To aid in the application-specific implementation of auto-phasing and line
synchronization functions, the GS9060 will generate a FIFO load pulse to reset
line-based FIFO storage.
The FIFO_LD output pin will normally be HIGH but will go LOW for one PCLK
period, thereby generating a FIFO write reset signal.
The FIFO load pulse will be generated such that it is co-timed to the SAV XYZ code
word presented to the output data bus. This ensures that the next PCLK cycle will
correspond to the first active sample of the video line.
Figure 3-5 shows the timing relationship between the FIFO_LD signal and the
output video data.
PCLK
3FF
000
000
CHROMA DATA OUT
XYZ
(SAV)
LUMA DATA OUT
FIFO_LD
FIFO LOAD PULSE – 20BIT OUTPUT MODE
PCLK
MULTIPLEXED
Y/Cr/Cb DATA OUT
XYZ
(SAV)
000
000
3FF
FIFO_LD
FIFO LOAD PULSE – 10BIT OUTPUT MODE
Figure 3-5: FIFO_LD Pulse Timing
22208 - 8 January 2007
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