GS1560A/GS1561 Data Sheet
3.12.3 Configuration and Status Registers
Table 3-17 summarizes the GS1560A/GS1561's internal status and configuration
registers.
All of these registers are available to the host via the GSPI and are all individually
addressable.
Where status registers contain less than the full 16 bits of information however, two
or more registers may be combined at a single logical address.
Table 3-17: GS1560A internal registers
Address
Register Name
See Section
000h
IOPROC_DISABLE
ERROR_STATUS
EDH_FLAG
Section 3.10.6
Section 3.10.5
Section 3.10.7
Section 3.10.4
Section 3.10.2.1
Section 3.10.3
Section 3.10.4
Section 3.10.5.2
Section 3.10.5
001h
003h
004h
VIDEO_STANDARD
ANC_TYPE
005h - 009h
00Ch - 00Dh
00Eh - 011h
012h - 019h
01Ah
VIDEO_FORMAT
RASTER_STRUCTURE
EDH_CALC_RANGES
ERROR_MASK
3.13 JTAG
When the JTAG/HOST input pin of the GS1560A/GS1561 is set HIGH, the host
interface port will be configured for JTAG test operation. In this mode, pins 27
through 30 become TMS, TDO, TDI, and TCK. In addition, the RESET_TRST pin
will operate as the test reset pin.
Boundary scan testing using the JTAG interface will be enabled in this mode.
There are two methods in which JTAG can be used on the GS1560A/GS1561:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power on self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other
devices driving the digital I/O pins. If the tests are to be applied only at ATE, this
can be accomplished with tri-state buffers used in conjunction with the
JTAG/HOST input signal. This is shown in Figure 3-14.
27360 - 8 September 2005
70 of 80
GENNUM [ GENNUM CORPORATION ]
