GS1560A/GS1561 Data Sheet
As described in Data Through Mode on page 46, the data bus outputs will be
forced to logic LOW if the device is set to operate in master mode but cannot
identify SMPTE TRS ID or DVB-ASI sync words in the input data stream.
3.11.5 Parallel Output Clock (PCLK)
The frequency of the PCLK output signal of the GS1560A/GS1561 is determined
by the output data format. Table 3-16 below lists the possible output signal formats
and their corresponding parallel clock rates. Note that DVB-ASI output will always
be in 10-bit format, regardless of the setting of the 20bit/10bit pin.
Table 3-16: Parallel Data Output Format
Status / Control Signals*
Output Data Format
SMPTE MODE
DOUT
[19:10]
DOUT
[9:0]
PCLK
20bit/
10bit
SD/HD SMPTE_BYPASS DVB_ASI
20bit DEMULTIPLEXED SD
10bit MULTIPLEXED SD
LUMA
CHROMA
13.5MHz
27MHz
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LUMA /
CHROMA
FORCED
LOW
20bit DEMULTIPLEXED HD
10bit MULTIPLEXED HD
LUMA
CHROMA
74.25 or
74.25/
1.001MHz
HIGH
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LUMA /
CHROMA
FORCED
LOW
148.5 or
148.5/
1.001MHz
DVB-ASI MODE
10bit DVB-ASI
DVB-ASI
DATA
FORCED
LOW
27MHz
27MHz
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
DVB-ASI
DATA
FORCED
LOW
DATA-THROUGH MODE**
20bit DEMULTIPLEXED SD
10bit MULTIPLEXED SD
DATA
DATA
13.5MHz
27MHz
HIGH
LOW
HIGH
HIGH
LOW
LOW
LOW
LOW
DATA
FORCED
LOW
20bit DEMULTIPLEXED HD
10bit MULTIPLEXED HD
DATA
DATA
74.25 or
74.25/
1.001MHz
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DATA
FORCED
LOW
148.5 or
148.5/
1.001MHz
*NOTE1: Recall that SD/HD, SMPTE_BYPASS, and DVB_ASI are input control pins in slave mode to be set by the application layer, but are
output status signals set by the device in master mode.
**NOTE 2: Data-Through mode is only available in slave mode Data Through Mode on page 46.
27360 - 8 September 2005
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