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GS1561-CFE3 参数 Datasheet PDF下载

GS1561-CFE3图片预览
型号: GS1561-CFE3
PDF下载: 下载PDF文件 查看货源
内容描述: GS1560A / GS1561 HD - LINX -R II双率解串器 [GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer]
分类和应用: 存储静态存储器
文件页数/大小: 80 页 / 1307 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS1560A/GS1561 Data Sheet  
3.12 GSPI Host Interface  
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to  
allow the host to enable additional features of the device and /or to provide  
additional status information through configuration registers in the  
GS1560A/GS1561.  
The GSPI comprises a serial data input signal SDIN, serial data output signal  
SDOUT, an active low chip select CS, and a burst clock SCLK. The burst clock  
must have a duty cycle between 40% and 60%.  
Because these pins are shared with the JTAG interface port, an additional control  
signal pin JTAG/HOST is provided. When JTAG/HOST is LOW, the GSPI interface  
is enabled.  
When operating in GSPI mode, the SCLK, SDIN, and CS signals are provided by  
the host interface. The SDOUT pin is a high-impedance output allowing multiple  
devices to be connected in parallel and selected via the CS input. The interface is  
illustrated in Figure 3-9.  
All read or write access to the GS1560A/GS1561 is initiated and terminated by the  
host processor. Each access always begins with a 16-bit command word on SDIN  
indicating the address of the register of interest. This is followed by a 16-bit data  
word on SDIN in write mode, or a 16-bit data word on SDOUT in read mode.  
Application Host  
SCLK  
GS1560A / GS1561  
SCLK  
SDOUT  
SDIN  
CS  
CS  
SDIN  
SDOUT  
Figure 3-9: Gennum Serial Peripheral Interface (GSPI)  
3.12.1 Command Word Description  
The command word is transmitted MSB first and contains a read/write bit, nine  
reserved bits and a 6-bit register address. Set R/W = '1' to read and R/W = '0' to  
write from the GSPI.  
Command words are clocked into the GS1560A/GS1561 on the rising edge of the  
serial clock SCLK. The appropriate chip select, CS, signal must be asserted low a  
minimum of 1.5ns (t in Figure 3-12 and Figure 3-13) before the first clock edge to  
0
ensure proper operation.  
Each command word must be followed by only one data word to ensure proper  
operation.  
27360 - 8 September 2005  
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