serial digital input 1 (DDI1 / DDI1) is selected as the input to the GS1559's reclocker
stage. When IP_SEL is set LOW, serial digital input 2 (DDI2 / DDI2) is selected.
4.2.2 Carrier Detect Input
For each of the differential inputs, an associated Carrier Detect input signal is included,
(CD1 and CD2). These signals are generated by Gennum's family of automatic cable
Equalizers.
When LOW, CDx indicates that a valid serial digital data stream is being delivered to the
GS1559 by the Equalizer. When HIGH, the serial digital input to the device should be
considered invalid. If no Equalizer precedes the device, the application layer should set
CD1 and CD2 accordingly.
A 2x1 input Multiplexer is also provided for these signals. The internal
CARRIER_DETECT signal is determined by the setting of the IP_SEL pin and is used by
the lock detect block of the GS1559 to determine the lock status of the device, (see Lock
Detect on page 29).
4.2.3 Single Input Configuration
If the application requires a single differential input, the DDI pin for the second set of
inputs and the associated carrier detect should be tied HIGH. The DDI pin may be left
unconnected, and the termination pin should be AC terminated to ground.
4.3 Serial Digital Reclocker
The output of the 2x1 serial digital input Multiplexer passes to the GS1559's internal
reclocker stage. The function of this block is to lock to the input data stream, extract a
clean clock, and retime the serial digital data to remove high frequency jitter.
The Reclocker was designed with a 'hexabang' Phase and Frequency Detector. That is,
the PFD used can identify six 'degrees' of phase/frequency misalignment between the
input data stream and the clock signal provided by the VCO, and correspondingly signal
the Charge Pump to produce six different control voltages. This results in fast and
accurate locking of the PLL to the data stream.
In Master mode, the operating center frequency of the Reclocker is toggled between
270Mb/s and 1.485Gb/s by the Lock Detect block, (see Lock Detect on page 29). In Slave
mode, however, the center frequency is determined entirely by the SD/HD input control
signal set by the application layer.
If lock is achieved, the Reclocker provides an internal PLL_LOCK signal to the Lock
Detect block of the device.
4.3.1 External VCO
The GS1559 requires the external GO1555/GO1525* Voltage Controlled Oscillator as
part of the reclocker's phase-locked loop. This external VCO implementation was
chosen to ensure high quality reclocking.
GS1559 HD-LINX™ II Multi-Rate Deserializer with
Loop-Through Cable Driver
Data Sheet
26 of 71
30572 - 8
July 2008
GENNUM [ GENNUM CORPORATION ]
