GL9701 PCI ExpressTM to PCI Bridge
Low Clamp
Current
-3 < Vin ≤-1
-25+(Vin+1)/0.015
mA
mA
Icl
High Clamp
Current
Vcc+4 > Vin ≥Vcc+1 25+(Vin-Vcc-1)/0.015
Ich
Output Rise
Slew Rate
Output Fall
Slew Rate
0.2Vcc - 0.6Vcc load
0.6Vcc - 0.2Vcc load
1
1
4
4
V/ns
V/ns
3
3
slewr
slewf
7.6 Clock and Reset Specifications
Symbol
Tcyc
Parameter
Min
30
Max
Units
ns
Notes
CLK Cycle Time
CLK High Time
∞
1
11
ns
Thigh
CLK Low Time
CLK Slew Rate
RST#SlewRate
11
1
ns
Tlow
4
-
V/ns
2
3
-
-
50
mV/ns
Notes:
1. In general, all PCI components must work with any clock frequency between nominal DC and 33 MHz.
Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by
testing. The clock frequency may be changed at any time during the operation of the system so long as the
clock edges remain "clean" (monotonic) and the minimum cycle and high and low times are not violated. For
example, the use of spread spectrum techniques to reduce EMI emissions is included in this requirement.
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