GL9701 PCI ExpressTM to PCI Bridge
Refer to Section 7.6.4.1 for the spread spectrum requirements for 66 MHz. The clock may only be stopped in a
low state. A variance on this
specification is allowed for components designed for use on the system board only. These components may
operate at any single fixed frequency up to 33 MHz and may enforce a policy of no frequency changes.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across
the minimum peak-to-peak portion of the clock waveform as shown in Figure 4-7.
3. The minimum RST# slew rate applies only to the rising (deassertion) edge of the reset signal and ensures that
system noise cannot render an otherwise monotonic signal to appear to bounce in the switching range. RST#
waveforms and timing are discussed in Section 4.3.2.
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