GL9701 PCI ExpressTM to PCI Bridge
by eventually resulting
in only one
Downstream and one
Upstream Port.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load and measured using the
clock recovery function.
3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of
TTX-JITTER-MAX = 0.25 UI for the Transmitter using the clock recovery function. The
TTX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the
maximum deviation from the median is less than half of the total TX jitter budget using the clock recovery
function. It should be noted that the median is not the same as the mean. The jitter median describes the point
in time where the number of jitter points on either side is approximately equal as opposed to the averaged time
value. This parameter is measured with the equivalent of a zero jitter reference clock. The TTX-EYE
measurement is to be met at the target bit error rate. The TTX-EYE-MEDIAN-to-MAX-JITTER is to be met
using the compliance pattern at a sample size of 1,000,000 UI.
4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 10 dB with a
differential test input signal no less than 200 mV (peak value, 400 mV differential peak to peak) swing around
ground applied to D+ and D- lines and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance
requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to
ground for both the D+ and D- line. Note that the series capacitors CTX is optional for the return loss
measurement.
5. Measured between 20-80% at Transmitter package pins into a test load for both VTX-D+ and VTX-D-.
6. ZTX-DIFF-DC is the small signal resistance of the transmitter measured at a DC operating point that is
equivalent to that established by connecting a 100 Ω resistor from D+ and D- while the TX is driving a static
logic one or logic zero. Equivalently, this parameter can be derived by measuring the RMS voltage of the TX
while transmitting a test pattern into two different differential terminations that are
near 100 Ω. Small signal resistance is measured by forcing a small change in differential voltage and dividing
this by the corresponding change in current.
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