GL9701 PCI ExpressTM to PCI Bridge
Capacitance
IDSEL Pin
8
pF
4
CIDSEL
Capacitance
Pin Inductance
20
1
nH
5
6
Lpin
IOff
PME# input leakage Vo ≦ 3.6 V
-
μA
Vcc off or
floating
Notes:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are
calculated to pull a floated network. Applications sensitive to static power utilization must assure that the
input buffer is conducting minimum current at this input voltage.
2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK, SMBDAT, and SMBCLK) with
an exception granted to system board-only devices up to 16 pF in order to accommodate PGA packaging. This
would mean, in general, that components for add-in cards need to use alternatives to ceramic PGA packaging;
i.e., PQFP, SGA, etc. Pin capacitance for SMBCLK and SMBDAT is not specified; however, the maximum
capacitive load is specified for the add-in card in Section 8.2.5.
4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
5. This is a recommendation, not an absolute requirement. The actual value should be provided with the
component data sheet.
6. This input leakage is the maximum allowable leakage into the PME# open drain driver when power is
removed from Vcc of the component. This assumes that no event has occurred to cause the device to attempt
to assert PME#.
7.5 PCI Interface AC Specifications
Symbol
Ioh(AC)
Parameter
Condition
Min.
-12Vcc
Max
Units
mA
Notes
Switching
0 < Vout ≦0.3Vcc
1
Current High
0.3Vcc<Vout<0.9Vcc
0.7Vcc < Vout < Vcc
-17.1(Vcc-Vout)
mA
1
Eqt'n C
1, 2
Switching
Vcc >Vout ≧0.6Vcc
16Vcc
mA
mA
1
Iol(AC)
Current Low
0.6Vcc>Vout>0.1Vcc
0.18Vcc>Vout>0
26.7Vout
1
Eqt'n D
1, 2
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