GL9701 PCI ExpressTM to PCI Bridge
is not the same as the mean. The jitter median describes the point in time where the number of jitter points on
either side is approximately equal as opposed to the averaged time value.
The RX UI recovered using the clock recovery function must be used as the reference for the eye diagram.
This parameter is measured with the equivalent of a zero jitter reference clock. The TRX-EYE measurement is
to be met at the target bit error rate. The TRX-EYE-MEDIAN-to-MAX-JITTER specification is to be met
using the compliance pattern at a sample size of 1,000,000 UI.
10. See the PCI Express Jitter and BER white paper for more details on the Rx-Eye measurement.
11. The Receiver input impedance shall result in a differential return loss greater than or equal to 10 dB with a
differential test input signal of no less than 200 mV (peak value, 400 mV differential peak to peak) swing
around ground applied to D+ and D- lines and a common mode return loss greater than or equal to 6 dB (no
bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to
all valid input levels. The reference impedance for return loss measurements for is 50 Ω to ground for both
the D+ and D- line. Note that the series capacitors CTX is optional for the return loss measurement.
12. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state
of the LTSSM) there is a 5 ms transition time before Receiver termination values must be met on all
un-configured Lanes of a Port.
13. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is
asserted. This helps ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on
when it is not. This term must be measured at 200 mV above the RX ground.
7.4 PCI Interface DC Specifications
Symbol
Parameter
Condition
Min.
Max
Units
Notes
Supply Voltage
Input High Voltage
Input Low Voltage
3.0
0.5Vcc
-0.5
3.6
V
V
V
Vcc
Vih
Vil
Vcc + 0.5
0.3Vcc
Input Pull-up
Voltage
0.7Vcc
0.9Vcc
5
V
1
2
Vipu
Input Leakage
Current
0 < Vin < Vcc
+10
μA
Iil
Output High Voltage Iout = -500μA
Output Low Voltage Iout = 1500μA
Input Pin
V
V
Voh
Vol
Cin
0.1Vcc
10
pF
3
Capacitance
CLK Pin
12
pF
Cclk
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