GL9701 PCI ExpressTM to PCI Bridge
4:0
ROS
00h
Secondary Uncorrectable First Error Pointer
6.55 Offset 13ch: Secondary Header Log Register
Bits
Type
Default
Description
Transaction Attribute – Not supported.
35:0
ROS
0h
Transaction Command Lower – The 4-bit value transferred on
39:36
ROS
0h
C/BE[3:0]# during the first address
phase.
Transaction Command Upper – Not supported
43:40
ROS
ROS
0h
0h
Transaction Address – bits 127:96 will be set to zero
127:64
6.56 Offset 150h: Device Serial Number Enhanced Capability Header Register
Bits
15:0
Type
RO
Default
0003h
1h
Description
PCI Express Extended Capability ID
Capability Version
19:16
31:20
RO
RO
000h
Next Capability Offset
6.57 Offset 154h: Device Serial Number Register
Bits
Type
Default
Description
63:0
RO
0h
PCI Express Device Serial Number
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