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GL9701-MXG 参数 Datasheet PDF下载

GL9701-MXG图片预览
型号: GL9701-MXG
PDF下载: 下载PDF文件 查看货源
内容描述: PCI ExpressTM至PCI桥 [PCI ExpressTM to PCI Bridge]
分类和应用: 微控制器和处理器外围集成电路uCs集成电路uPs集成电路PC
文件页数/大小: 75 页 / 1051 K
品牌: GENESYS [ GENESYS LOGIC ]
 浏览型号GL9701-MXG的Datasheet PDF文件第56页浏览型号GL9701-MXG的Datasheet PDF文件第57页浏览型号GL9701-MXG的Datasheet PDF文件第58页浏览型号GL9701-MXG的Datasheet PDF文件第59页浏览型号GL9701-MXG的Datasheet PDF文件第61页浏览型号GL9701-MXG的Datasheet PDF文件第62页浏览型号GL9701-MXG的Datasheet PDF文件第63页浏览型号GL9701-MXG的Datasheet PDF文件第64页  
GL9701 PCI ExpressTM to PCI Bridge  
Delayed Transaction Discard Timer Expired  
10  
RWS  
1
Mask  
PERR# Assertion Detected Mask  
11  
12  
13  
RWS  
RWS  
RWS  
0
1
0
SERR# Assertion Detected Mask  
Internal Bridge Error Mask  
6.53 Offset 134h: Secondary Uncorrectable Error Severity Register  
Bits  
0
Type  
RWS  
RWS  
RWS  
RWS  
RsvdP  
RWS  
Default  
Description  
Target-Abort on Split Completion Severity  
Master-Abort on Split Completion Severity  
Received Target-Abort Severity  
Received Master-Abort Severity  
Reserved  
0
0
0
0
0
0
1
2
3
4
Unexpected Split Completion Error Severity  
5
Uncorrectable Split Completion Message Data  
Error Severity  
6
RWS  
1
Uncorrectable Data Error Severity  
7
8
9
RWS  
RWS  
RWS  
0
1
1
Uncorrectable Attribute Error Severity  
Uncorrectable Address Error Severity  
Delayed Transaction Discard Timer Expired  
Severity  
10  
RWS  
0
PERR# Assertion Detected Severity  
11  
12  
13  
RWS  
RWS  
RWS  
0
1
0
SERR# Assertion Detected Severity  
Internal Bridge Error Severity  
6.54 Offset 138h: Secondary Error Capabilities and Control Register  
Bits  
Type  
Default  
Description  
©2000-2006 Genesys Logic Inc. - All rights reserved.  
Page 60  
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