GL9701 PCI ExpressTM to PCI Bridge
0
6
RWS
RWS
RWS
RWS
RWS
0
0
0
0
0
Receiver Error Mask
Bad TLP Mask
7
Bad DLLP Mask
8
REPLAY_NUM Rollover Mask
Replay Timer Timeout Mask
12
6.49 Offset 118h: Advanced Error Capabilities and Control Register
Bits
Type
Default
Description
First Error Pointer – Identifies the bit position of the first error
4:0
ROS
00h
reported in the Uncorrectable Error Status register.
ECRC Generation Capable – This bit indicates that
the device is capable of generating ECRC.
ECRC Generation Enable – This bit when set
enables ECRC generation.
5
6
7
8
RO
RWS
RO
1b
0b
1b
0b
ECRC Check Capable – This bit indicates that the
device is capable of checking ECRC.
ECRC Check Enable – This bit when set enables
ECRC checking.
RWS
6.50 Offset 11ch: Header Log Register
Bits
Type
Default
Description
127:0
ROS
0h
Header Log – Header of TLP associated with error
6.51 Offset 12ch: Secondary Uncorrectable Error Status Register
Bits
0
Type
Default
Description
Target-Abort on Split Completion Status
Master-Abort on Split Completion Status
Received Target-Abort Status
RW1CS
RW1CS
RW1CS
0
0
0
1
2
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