MB90560/565 Series
• Block diagram
Interrupt request signal #11 (0BH) *
Rese-
A/D control status register
(ADCS0, ADCS1)
BUSY INT INTE PAUS STS1 STS0 STRT
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
rved
6
2
16-bit reload timer 1 output
Decoder
Clock selector
16-bit freerun timer zero-detect
φ
Comparator
Sample &
P57/AN7
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1
P50/AN0
Control circuit
hold circuit
Analog
channel
selector
2
2
AVR
AVCC
AVSS
D/A converter
A/D data register
(ADCR0, ADCS1)
S10 ST1 ST0 CT1 CT0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
φ : Machine clock
* : Interrupt number
51
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