VNCLO-PSU-EU 参数 Datasheet PDF下载

Document Reference No.: FT_000327

Vinculo Development Module Datasheet Version 1.0

Clearance No.: FTDI#173

4.3 Parallel FIFO Interface - Asynchronous Mode

The Parallel FIFO Asynchronous mode is functionally the same as the Parallel FIFO Interface available in

the FTDI VDIP1 module and has an eight bit data bus, individual read and write strobes and two

hardware flow control signals.

4.3.1 Signal Description - Parallel FIFO Interface

The Parallel FIFO Interface signals can be programmed to a choice of available I/O pins.

shows the Parallel FIFO Interface signals and the pins that they can be mapped. Details of the operation

and timing can be found in the VNC2 datasheet.

Available Pins

Name

Type

Description

J3-5, J6-7, J7-1, J7-5

J3-6, J6-1, J6-4, J6-8, J7-2, J7-6

J3-3, J3-7, J4-1, J6-2, J6-5, J7-3, J7-7

J3-4, J3-8, J4-2, J6-3, J6-6, J7-4, J7-8

J3-5, J6-7, J7-1, J7-5

J3-6, J6-1, J6-4, J6-8, J7-2, J7-6

J3-3, J3-7, J4-1, J6-2, J6-5, J7-3, J7-7

J3-4, J3-8, J4-2, J6-3, J6-6, J7-4, J7-8

fifo_data[0]

fifo_data[1]

fifo_data[2]

fifo_data[3]

fifo_data[4]

fifo_data[5]

fifo_data[6]

fifo_data[7]

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

FIFO data bus Bit 0

FIFO data bus Bit 1

FIFO data bus Bit 2

FIFO data bus Bit 3

FIFO data bus Bit 4

FIFO data bus Bit 5

FIFO data bus Bit 6

FIFO data bus Bit 7

When high, do not read data from the FIFO.

When low, there is data available in the FIFO

which can be read by strobing RD# low, then

high.

When high, do not write data into the FIFO.

When low, data can be written into the FIFO

by strobing WR high, then low.

Enables the current FIFO data byte on

D0...D7 when low. Fetches the next FIFO

data byte (if available) from the receive FIFO

buffer when RD# goes from high to low

J3-5, J6-7, J7-1, J7-5

fifo_rxf#

Output

J3-6, J6-1, J6-4, J6-8, J7-2, J7-6

fifo_txe#

Output

J3-3, J3-7, J4-1, J6-2, J6-5, J7-3, J7-7

fifo_rd#

Input

Writes the data byte on the D0...D7 pins into

the transmit FIFO buffer when WR goes from

Input

high to low.

Table 4.4 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface

J3-4, J3-8, J4-2, J6-3, J6-6, J7-4, J7-8

fifo_wr#

Note: # defines active low signals.

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