Document Reference No.: FT_000327
Vinculo Development Module Datasheet Version 1.0
Clearance No.: FTDI#173
4
Configurable Pin outs
4.1 UART Interface
When the Vinculo data and control buses are configured as a UART interface, the interface implements a
standard asynchronous serial UART port with flow control. The UART can support baud rates from
300baud to 6Mbaud. The UART interface is described in more detail in the Vinculum-II datasheet please
refer to: -
4.1.1
Signal Description – UART Interface
The UART signals can be programmed to a choice of available I/O pins.
explains the available
pins for each of the UART signals. This is a subset of what the VNC2-64Q is capable of to avoid conflict
with other functions on the Vinculo module.
Available Pins
Name
Type
Description
J3-2, J3-5, J6-7, J7-1, J7-5
uart_txd
Output
Transmit asynchronous data output
(Default J3-2)
Receive asynchronous data input
(Default J3-1)
Request To Send Control Output
Clear To Send Control Input
Data Acknowledge (Data Terminal
Ready Control) Output
Data Request (Data Set Ready
Control) Input
Data Carrier Detect Control Input
Ring Indicator Control Input. RI# low
can be used to resume the PC USB
Host controller from suspend.
Enable Transmit Data for RS485
designs.
TXDEN
may be used to
signal that a transmit operation is in
progress. The TXDEN signal will be
set high one bit-time before data is
transmitted and return low one bit
time after the last bit of a data frame
has been transmitted
J3-1, J3-6, J6-1, J6-4, J6-8, J7-2, J7-6
J3-3, J3-7, J4-1, J6-2, J6-5, J7-3, J7-7
J3-4, J3-8, J4-2, J6-3, J6-6, J7-4, J7-8
J3-2, J3-5, J6-7, J7-1, J7-5
J3-1, J3-6, J6-1, J6-4, J6-8, J7-2, J7-6
J3-3, J3-7, J4-1, J6-2, J6-5, J7-3, J7-7
J3-4, J3-8, J4-2, J6-3, J6-6, J7-4, J7-8
uart_rxd
uart_rts#
uart_cts#
uart_dtr#
uart_dsr#
uart_dcd#
uart_ri#
Input
Output
Input
Output
Input
Input
Input
J3-2, J3-5, J6-7, J7-1, J7-5
uart_tx_active
Output
Table 4.1 - Data and Control Bus Signal Mode Options – UART
Note: # defines active low signals.
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9
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