Document Reference No.: FT_000327
Vinculo Development Module Datasheet Version 1.0
Clearance No.: FTDI#173
4.2 Serial Peripheral Interface (SPI)
The VNC2-64Q has one master module and two slave modules. These modules are described more fully in
a
VNC2
datasheet please refer to: -
4.2.1 Signal Description - SPI Slave
The SPI Slave signals can be programmed to a choice of available I/O pins.
explains the
available pins for each of the SPI Slave signals. This is a subset of what the VNC2-64Q is capable of to
avoid conflict with other functions on the Vinculo module.
Name
Available Pins
Type
Description
J3-5, J6-7, J7-1, J7-5
spi_s0_clk
spi_s1_clk
spi_s0_mosi
Input
Slave clock input
Input/Output
Master Out Slave In
Synchronous data from master to slave
J3-6, J6-1, J6-4, J6-8, J7-2, J7-6
spi_s1_mosi
spi_s0_miso
spi_s1_miso
spi_s0_ss#
Input
Output
J3-3, J3-7, J4-1, J6-2, J6-5, J7-3, J7-7
Master In Slave Out
Synchronous data from slave to master
Slave chip select
J3-4, J3-8, J4-2, J6-3, J6-6, J7-4, J7-8
spi_s1_ss#
Table 4.2 - Data and Control Bus Signal Mode Options – SPI Slave
Note: # defines active low signals.
4.2.2 Signal Description - SPI Master
The SPI Master signals can be programmed to a choice of available I/O pins.
shows the SPI
master signals and the available pins that they can be mapped.
This is a subset of what the VNC2-64Q is
capable of to avoid conflict with other functions on the Vinculo module.
Available Pins
Name
Type
Description
J3-5, J4-6, J6-7, J7-1, J7-5
spi_m_clk
Output
SPI master clock input
(J4-6 is the default)
spi_m_mosi
J3-6, J4-4, J6-1, J6-4, J6-8, J7-2, J7-6
Output
Master Out Slave In
Synchronous data from master to slave
(J4-4 is the default)
spi_m_miso
J3-3, J3-7, J4-1, J4-5, J6-2, J6-5, J7-3,
J7-7
spi_m_ss_0#
Input
Master In Slave Out
Synchronous data from slave to master
(J4-5 is the default)
J3-4, J3-8, J4-2, J4-3, J6-3, J6-6, J7-4,
J7-8
3-5, J6-7, J7-1, J7-5
Output
Active low slave select 0 from master to slave
0
This SS# is used with the onboard ADC
spi_m_ss_1#
Output
Active low slave select 1 from master to slave
1
Table 4.3 - Data and Control Bus Signal Mode Options – SPI Master
Note: # defines active low signals.
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