Document Reference No.: FT_000016
VDIP1 Vinculum VNC1L Module Datasheet Version 1.01
Clearance No.: FTDI# 131
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3.7.1 Timing Diagram – Parallel FIFO Read Transaction
When in parallel FIFO interface mode, the timing of a read is shown in
and
Figure 3.6 - FIFO Read Cycle.
Time
T1
T2
T3
T4
T5
T6
Description
RD# Active Pulse Width
RD# to RD# Pre-Charge Time
RD# Active to Valid Data*
Valid Data Hold Time from RD#
Inactive*
RD# Inactive to RXF#
RXF# Inactive After RD# Cycle
Min
50
50 + T6
20
0
0
80
Max
-
-
50
-
25
-
Unit
ns
ns
ns
ns
ns
ns
Table 3.9 FIFO Read Cycle Timing
* Load = 30pF
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