VDIP1_10 参数 Datasheet PDF下载

Document Reference No.: FT_000016

VDIP1 Vinculum VNC1L Module Datasheet Version 1.01

Clearance No.: FTDI# 131

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3.6.2 SPI Slave Data Write Cycle

When in SPI mode, the timing of a write operation is shown in

Figure 3.4 – SPI Slave Data Write Cycle.

From Start - SPI CS must be held high for the entire write cycle, and must be taken low for at least

one clock period after t he write is co mpletedThe. first bit on SPI Data In is the R/W bit - inputting

a ‘0’ here a llows data to be written to the chip. The next bit is the address bit, ADD, which is used

to indicate whether the data register (‘0’) or the status register (‘1’) is written to. During the SPI

write cycle a byte of data can be input to SPI Data In on the next clock cycle after t he address bit,

MSBAfterfirst.t he data has been clocked in to the chip, t he status of SPI Data Out should be

checked to see if the data read was accepted. A ‘0’ level on SPI Data Out means that the data

write was accepted. A ‘1’ indicates that the internal buffer is full, and the write should be repeated.

Remember that CS must be held low for at least one clock period before being taken high again to

continue with the next read or write cycle.

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