Document Reference No.: FT_000016
VDIP1 Vinculum VNC1L Module Datasheet Version 1.01
Clearance No.: FTDI# 131
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3.7 Signal Descriptions - Parallel FIFO Interface
The Parallel FIFO interface I/O pin description of the VNC1L device is shown in
Pin No.
6
8
9
10
11
12
13
14
D0
D1
D2
D3
D4
D5
D6
D7
Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Type
FIFO Data Bus Bit 0
FIFO Data Bus Bit 1
FIFO Data Bus Bit 2
FIFO Data Bus Bit 3
FIFO Data Bus Bit 4
FIFO Data Bus Bit 5
FIFO Data Bus Bit 6
FIFO Data Bus Bit 7
When high, do not read data from the FIFO. When low, there is data
available in the FIFO which can be read by stro bing RD# low, t hen
high again.
When high, do not write data into the FIFO. When low, data can be
written into the FIFO by strobing WR high, then low.
Enables the current
FIFO data byte on D0...D7 when low. Fetched the
next FIFO data byte (if avail- able) fro m the recei ve FIFO buffer w hen
RD# goes fro m high to low
Description
15
16
RXF#
TXE#
OUTPUT
OUTPUT
17
RD#
INPUT
Writes the data byte on the D0...D7 pins into the transmit FIFO buffer
19
WR
INPUT
when WR goes from high to low.
Table 3.8 - Default Interface I/O Pin Configuration Option – Paralle FIFO Interface
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