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DS_FT313H 参数 Datasheet PDF下载

DS_FT313H图片预览
型号: DS_FT313H
PDF下载: 下载PDF文件 查看货源
内容描述: 该FT313H是一个高速通用串行总线( USB )主机控制器,通用串行总线规范2.0版兼容,并支持高达480M bit / s的数据传输速度。 [The FT313H is a Hi-Speed Universal Serial Bus (USB) Host Controller compatible with Universal Serial Bus Specification Rev 2.0 and supports data transfer speeds of up to 480M bit/s.]
分类和应用: 数据传输控制器
文件页数/大小: 64 页 / 1588 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document No.: FT_000589  
FT313H USB2.0 HS Host Controller Datasheet Version 1.1  
Clearance No.: FTDI# 318  
5.2.7 FRINDEX register (address = 1Ch)  
This register is used by the host controller to index into the periodic frame. The register updates very 125  
microseconds (one each micro-frame).  
Bit  
Name  
Type  
RO  
Default value  
28’h0  
Description  
[31:14]  
[13:0]  
Reserved  
FRINDEX  
-
Frame Index  
R/W  
14’b0  
This register is used by the host controller to  
index the frame into the Periodic Frame List. It  
updates every 125 microseconds. This register  
cannot be written unless the host controller is  
at the halted state.  
Bits[N:3] are used for Frame List current  
index. This means that each location of the  
frame list is accessed 8 times before moving  
to the next index.  
USBCMD[Frame List Size] Number Elements N  
00b  
01b  
10b  
11b  
(1024)  
(512)  
(256)  
12  
11  
10  
Reserved  
Table 5-8 Frame index register  
5.2.8 PERIODICLISTADDR register (address = 24h)  
This 32-bit register contains the beginning address of the periodic frame list in the system memory.  
Bit  
Name  
Type  
Default value  
Description  
Periodic Frame List Base Address  
[31:12]  
PERI_BASEADR  
R/W  
20’h0  
This 32-bit register contains the beginning  
address of the  
Periodic Frame List in the system memory.  
These bits correspond to the memory address  
signals[31:12].  
[11:0]  
Reserved  
RO  
12’b0  
-
Table 5-9 Periodic frame list base address register  
5.2.9 ASYNCLISTADDR register (address = 28h)  
This 32-bit register contains the address of the next asynchronous queue head to be executed.  
Bit  
Name  
Type  
Default value  
Description  
Current Asynchronous List Address  
[31:5]  
ASYNC_LADR  
R/W  
27’h0  
This 32-bit register contains the address of the  
next asynchronous queue head to be  
executed. These bits correspond to the  
memory address signals [31:5].  
[4:0]  
Reserved  
RO  
5’b0  
-
Table 5-10 Current asynchronous list address register  
Copyright © 2012 Future Technology Devices International Limited  
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