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DS_FT313H 参数 Datasheet PDF下载

DS_FT313H图片预览
型号: DS_FT313H
PDF下载: 下载PDF文件 查看货源
内容描述: 该FT313H是一个高速通用串行总线( USB )主机控制器,通用串行总线规范2.0版兼容,并支持高达480M bit / s的数据传输速度。 [The FT313H is a Hi-Speed Universal Serial Bus (USB) Host Controller compatible with Universal Serial Bus Specification Rev 2.0 and supports data transfer speeds of up to 480M bit/s.]
分类和应用: 数据传输控制器
文件页数/大小: 64 页 / 1588 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document No.: FT_000589  
FT313H USB2.0 HS Host Controller Datasheet Version 1.1  
Clearance No.: FTDI# 318  
5.2.10  
POSTSC register (address = 30h)  
The port status and control register is in the power well. It is only reset by hardware when the power is  
initially applied or in response to a host controller reset. The initial conditions of a port are:  
No peripheral connected  
Port disable  
The software must not attempt to change the state of the port until the power is stable on the port. The  
host is required to have power stable to the port within 20 milliseconds of the zero to one transition.  
When a peripheral device is attached, the port state transitions to the connected state and system  
software will process this as with any status change notification.  
Bit  
Name  
Type  
Default value  
15’h0  
Description  
[31:17]  
16  
Reserved  
RO  
-
Test Force Enable  
TST_FORCEEN R/W  
1’b0  
When this signal is written as ‘1,’ the  
downstream facing port will be enabled in the  
high-speed mode. Then the Run/Stop bit must  
be transitioned to one in order to enable the  
transmission of the SOFs out of the port under  
test. This enables testing of the disconnect  
detection.  
[15:12]  
[11:10]  
Reserved  
LINE_STS  
RO  
RO  
4’b0  
-
Line Status  
2’b00  
These bits reflect the current logical levels of the  
D+ and D- signal lines.  
Bits[11:10] USB state  
00b  
10b  
01b  
11b  
SE0  
J-state  
K-state  
Undefined  
9
8
Reserved  
RO  
1’b0  
1’b0  
-
Port Reset  
PO_RESET  
R/W  
1 = Port is in the reset state.  
0 = Port is not in the reset state.  
When the software writes a ‘1’ to this bit, the  
bus reset sequence as defined in the USB  
specification will start.  
Software writes a ‘0’ to this bit to terminate the  
bus reset sequence. Software must keep this bit  
at a ‘1’ long enough to ensure the reset  
sequence.  
Note: Reset signal which shall be followed by the  
USB2.0 chapter 7.1.7.5 Reset Signal  
requirement. If detected HS device, the software  
shall wait more than 200us for port reset  
clearing. Before setting this bit, RUN/STOP bit  
should be set to ‘0.’  
Port Suspend  
7
PO_SUSP  
R/W  
1’b0  
1 = Port is in the suspend state  
0 = Port is not in the suspend state.  
Copyright © 2012 Future Technology Devices International Limited  
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