Document No.: FT_000589
FT313H USB2.0 HS Host Controller Datasheet Version 1.1
Clearance No.: FTDI# 318
Bit
Name
Type
Default value
Description
the PORTSC change bits.
USB Error Interrupt
1
USBERR_INT
R/WC
1’b0
The host controller sets this bit to ‘1’ when the
completion of a USB transaction results in an
error condition.
USB Interrupt
0
USB_INT
R/WC
1’b0
The host controller sets this bit to ‘1’ upon the
completion of a USB transaction.
Table 5-6 USB status register
5.2.6 USBINTR register (address = 18h)
This register enables and disables reporting of the corresponding interrupt to the software. When a bit is
set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that
are disabled in this register still appear in the USBSTS to allow the software to poll for events.
Bit
Name
Type
RO
Default value
26’h0
Description
[31:6]
5
Reserved
INT_OAA_EN
-
Interrupt on Async Advance Enable
R/W
1’b0
When this bit is set to ‘1,’ and the Interrupt on
Async Advance bit in the USBSTS register is
set to ‘1’ also, the host controller will issue an
interrupt at the next interrupt threshold.
Host System Error Enable
4
H_SYSERR_EN
FRL_ROL_EN
R/W
R/W
1’b0
When this bit is set to ‘1,’ and the Host
System Error Status bit in the USBSTS register
is set to ‘1’ also, the host controller will issue
an interrupt.
Frame List Rollover Enable
3
2
1
1’b0
1’b0
1’b0
When this bit is set to ‘1,’ and the Frame List
Rollover bit in the USBSTS register is set to ‘1’
also, the host controller will issue an interrupt.
Port Change Interrupt Enable
PO_CHG_DET_EN R/W
When this bit is set to ‘1,’ and the Port Change
Detect bit in the USBSTS register is set to ‘1’
also, the host controller will issue an interrupt.
USB Error Interrupt Enable
USBERR_INT_EN
USB_INT_EN
R/W
R/W
When this bit is set to ‘1,’ and the USBERRINT
bit in the USBSTS register is set to ‘1’ also, the
host controller will issue an interrupt at the
next interrupt threshold.
USB Interrupt Enable
0
1’b0
When this bit is set to ‘1,’ and the USBINT bit
in the USBSTS register is a set to ‘1’ also, the
host controller will issue an interrupt at the
next interrupt threshold. If set interrupt
threshold to 01h, means that when interrupt
event occurred, the INT signal will be toggled
at once.
Table 5-7 USB interrupt enable register
Copyright © 2012 Future Technology Devices International Limited
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