PCI Express
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the
TX UI.
NOTE
The reference impedance for return loss measurements is 50. to ground for
both the D+ and D– line (that is, as measured by a vector network analyzer
with 50-Ω probes—see Figure 50). Note that the series capacitors, CTX, are
optional for the return loss measurement.
V
= 0 mV
V
= 0 mV
RX-DIFF
RX-DIFF
(D+ D– Crossing Point)
(D+ D– Crossing Point)
V
> 175 mV
RX-DIFFp-p-MIN
0.4 UI = T
RX-EYE-MIN
Figure 49. Minimum Receiver Eye Timing and Voltage Compliance Specification
16.5.1 Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in Figure 50.
NOTE
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
D+ Package
Pin
C = C
TX
TX
Silicon
+ Package
C = C
TX
D– Package
Pin
R = 50 Ω
R = 50 Ω
Figure 50. Compliance Test/Measurement Load
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
76
Freescale Semiconductor
FREESCALE [ Freescale ]
