Serial RapidIO
17 Serial RapidIO
This section describes the DC and AC electrical specifications for the RapidIO interface of the
MPC8548E, for the LP-Serial physical layer. The electrical specifications cover both single- and
multiple-lane links. Two transmitters (short and long run) and a single receiver are specified for each of
three baud rates, 1.25, 2.50, and 3.125 GBaud.
Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to
driving two connectors across a backplane. A single receiver specification is given that will accept signals
from both the short- and long-run transmitter specifications.
The short-run transmitter should be used mainly for chip-to-chip connections on either the same
printed-circuit board or across a single connector. This covers the case where connections are made to a
mezzanine (daughter) card. The minimum swings of the short-run specification reduce the overall power
used by the transceivers.
The long-run transmitter specifications use larger voltage swings that are capable of driving signals across
backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications
allow a distance of at least 50 cm at all baud rates.
All unit intervals are specified with a tolerance of ±100 ppm. The worst case frequency difference between
any transmit and receive clock will be 200 ppm.
To ensure interoperability between drivers and receivers of different vendors and technologies, AC
coupling at the receiver input must be used.
17.1 DC Requirements for Serial RapidIO SD_REF_CLK and
SD_REF_CLK
For more information, see Section 15.2, “SerDes Reference Clocks.”
17.2 AC Requirements for Serial RapidIO SD_REF_CLK and
SD_REF_CLK
Table 54 lists the Serial RapidIO SD_REF_CLK and SD_REF_CLK AC requirements.
Table 54. SD_REF_CLK and SD_REF_CLK AC Requirements
Symbol
Parameter Description
REFCLK cycle time
Min
Typ
Max
Unit
Comments
t
—
10(8)
—
ns 8 ns applies only to serial
RapidIO with 125-MHz reference
clock
REF
t
t
REFCLK cycle-to-cycle jitter. Difference in the
period of any two adjacent REFCLK cycles.
—
—
—
80
40
ps
—
REFCJ
Phase jitter. Deviation in edge location with
respect to mean edge location.
–40
ps
—
REFPJ
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
77
FREESCALE [ Freescale ]
