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MPC8543EVUAQG 参数 Datasheet PDF下载

MPC8543EVUAQG图片预览
型号: MPC8543EVUAQG
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™III集成处理器硬件规格 [PowerQUICC™ III Integrated Processor Hardware Specifications]
分类和应用:
文件页数/大小: 144 页 / 1534 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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Serial RapidIO
17 Serial RapidIO
This section describes the DC and AC electrical specifications for the RapidIO interface of the
MPC8548E, for the LP-Serial physical layer. The electrical specifications cover both single- and
multiple-lane links. Two transmitters (short and long run) and a single receiver are specified for each of
three baud rates, 1.25, 2.50, and 3.125 GBaud.
Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to
driving two connectors across a backplane. A single receiver specification is given that will accept signals
from both the short- and long-run transmitter specifications.
The short-run transmitter should be used mainly for chip-to-chip connections on either the same
printed-circuit board or across a single connector. This covers the case where connections are made to a
mezzanine (daughter) card. The minimum swings of the short-run specification reduce the overall power
used by the transceivers.
The long-run transmitter specifications use larger voltage swings that are capable of driving signals across
backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications
allow a distance of at least 50 cm at all baud rates.
All unit intervals are specified with a tolerance of ±100 ppm. The worst case frequency difference between
any transmit and receive clock will be 200 ppm.
To ensure interoperability between drivers and receivers of different vendors and technologies, AC
coupling at the receiver input must be used.
17.1
DC Requirements for Serial RapidIO SD_REF_CLK and
SD_REF_CLK
For more information, see
17.2
AC Requirements for Serial RapidIO SD_REF_CLK and
SD_REF_CLK
Table 54. SD_REF_CLK and SD_REF_CLK AC Requirements
lists the Serial RapidIO SD_REF_CLK and SD_REF_CLK AC requirements.
Symbol
t
REF
Parameter Description
REFCLK cycle time
Min
Typ
10(8)
Max
Unit
ns
Comments
8 ns applies only to serial
RapidIO with 125-MHz reference
clock
t
REFCJ
t
REFPJ
REFCLK cycle-to-cycle jitter. Difference in the
period of any two adjacent REFCLK cycles.
Phase jitter. Deviation in edge location with
respect to mean edge location.
–40
80
40
ps
ps
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
77