PCI Express
15.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15-MHz range. The source impedance of the clock driver should be 50
Ω
to match the
transmission line and reduce reflections which are a source of noise to the system.
The detailed AC requirements of the SerDes reference clocks is defined by each interface protocol based
on application usage. Refer to the following sections for detailed information:
•
• Section 17.2, “AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK”
15.2.4.1
Spread Spectrum Clock
SD_REF_CLK/SD_REF_CLK are designed to work with a spread spectrum clock (+0% to –0.5%
spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,
a source without significant unintended modulation should be used.
15.3
SerDes Transmitter and Receiver Reference Circuits
SD_TXn
50
Ω
50
Ω
Transmitter
50
Ω
SD_TXn
SD_RXn
50
Ω
SD_RXn
shows the reference circuits for SerDes data lane’s transmitter and receiver.
Receiver
Figure 47. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below
(PCI Express, Serial Rapid IO, or SGMII) in this document based on the application usage:
•
•
Note that external an AC coupling capacitor is required for the above three serial transmission protocols
with the capacitor value defined in the specification of each protocol section.
16 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8548E.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
68
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FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
