High-Speed Serial Interfaces (HSSI)
shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8548E SerDes reference clock
input’s DC requirement.
HCSL CLK Driver Chip
CLK_Out
33
Ω
SD_REF_CLK
50
Ω
MPC8548E
Clock Driver
33
Ω
CLK_Out
100
Ω
Differential PWB Trace
SerDes Refer.
CLK Receiver
SD_REF_CLK
50
Ω
Total 50
Ω.
Assume clock driver’s
output impedance is about 16
Ω.
Clock driver vendor dependent
source termination resistor
Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the MPC8548E SerDes reference clock
input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
LVDS CLK Driver Chip
CLK_Out
10 nF
SD_REF_CLK
50
Ω
MPC8548E
Clock Driver
100
Ω
Differential PWB Trace
SerDes Refer.
CLK Receiver
CLK_Out
10 nF
SD_REF_CLK
50
Ω
Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
the MPC8548E SerDes reference clock input’s DC requirement, AC-coupling has to be used.
assumes that the LVPECL clock driver’s output impedance is 50
Ω.
R1 is used to DC-bias the LVPECL
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
66
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
