欢迎访问ic37.com |
会员登录 免费注册
发布采购

MPC8543EVUAQG 参数 Datasheet PDF下载

MPC8543EVUAQG图片预览
型号: MPC8543EVUAQG
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™III集成处理器硬件规格 [PowerQUICC™ III Integrated Processor Hardware Specifications]
分类和应用:
文件页数/大小: 144 页 / 1534 K
品牌: FREESCALE [ Freescale ]
 浏览型号MPC8543EVUAQG的Datasheet PDF文件第62页浏览型号MPC8543EVUAQG的Datasheet PDF文件第63页浏览型号MPC8543EVUAQG的Datasheet PDF文件第64页浏览型号MPC8543EVUAQG的Datasheet PDF文件第65页浏览型号MPC8543EVUAQG的Datasheet PDF文件第67页浏览型号MPC8543EVUAQG的Datasheet PDF文件第68页浏览型号MPC8543EVUAQG的Datasheet PDF文件第69页浏览型号MPC8543EVUAQG的Datasheet PDF文件第70页  
High-Speed Serial Interfaces (HSSI)  
Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It  
assumes that the DC levels of the clock driver chip is compatible with MPC8548E SerDes reference clock  
input’s DC requirement.  
HCSL CLK Driver Chip  
MPC8548E  
50 Ω  
SD_REF_CLK  
CLK_Out  
33 Ω  
33 Ω  
SerDes Refer.  
CLK Receiver  
100 Ω Differential PWB Trace  
Clock Driver  
CLK_Out  
SD_REF_CLK  
50 Ω  
Clock driver vendor dependent  
source termination resistor  
Total 50 Ω. Assume clock driver’s  
output impedance is about 16 Ω.  
Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)  
Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.  
Since LVDS clock driver’s common mode voltage is higher than the MPC8548E SerDes reference clock  
input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the  
LVDS output driver features 50-Ω termination resistor. It also assumes that the LVDS transmitter  
establishes its own common mode level without relying on the receiver or other external component.  
LVDS CLK Driver Chip  
MPC8548E  
50 Ω  
SD_REF_CLK  
CLK_Out  
10 nF  
SerDes Refer.  
CLK Receiver  
100 Ω Differential PWB Trace  
Clock Driver  
CLK_Out  
10 nF  
SD_REF_CLK  
50 Ω  
Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)  
Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.  
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with  
the MPC8548E SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 45  
assumes that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL  
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6  
66  
Freescale Semiconductor  
 复制成功!