High-Speed Serial Interfaces (HSSI)
400 mV < SD_REF_CLK Input Amplitude < 800 mV
SD_REF_CLK
SD_REF_CLK
0 V
Figure 42. Single-Ended Reference Clock Input DC Requirements
15.2.3 Interfacing With Other Differential Signaling Levels
•
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are
HCSL (high-speed current steering logic) compatible DC-coupled.
•
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the limited common mode input range allowed (100
to 400 mV) for DC-coupled connection.
•
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
NOTE
Figure 43 through Figure 46 below are for conceptual reference only. Due
to the fact that clock driver chip's internal structure, output impedance and
termination requirements are different between various clock driver chip
manufacturers, it’s very possible that the clock circuit reference designs
provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the MPC8548E SerDes reference clock receiver requirement
provided in this document.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
65
FREESCALE [ Freescale ]
