High-Speed Serial Interfaces (HSSI)
average voltage (common mode voltage) to be between 100 and 400 mV. Figure 40 shows the
SerDes reference clock input requirement for DC-coupled connection scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn). Figure 41 shows the SerDes reference clock
input requirement for AC-coupled connection scheme.
•
Single-ended mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
(single-ended swing) must be between 400 and 800 mV peak-to-peak (from V to V ) with
min
max
SD_REF_CLK either left unconnected or tied to ground.
— The SD_REF_CLK input average voltage must be between 200 and 400 mV. Figure 42 shows
the SerDes reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or
AC-coupled externally. For the best noise performance, the reference of the clock could be DC-
or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as
the clock input (SD_REF_CLK) in use.
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK
V
< 800 mV
max
100 mV < V < 400 mV
cm
SD_REF_CLK
V
> 0 V
min
Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK
V
< V + 400 mV
max cm
V
cm
SD_REF_CLK
V
> V – 400 mV
min cm
Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
64