High-Speed Serial Interfaces (HSSI)
outputs prior to AC-coupling. Its value could be ranged from 140 to 240 Ω depending on the clock driver
vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-Ω termination
resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8548E SerDes
reference clock’s differential input amplitude requirement (between 200 and 800 mV differential peak).
For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock
input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Consult a
clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular
clock driver chip.
LVPECL CLK Driver Chip
MPC8548E
50 Ω
SD_REF_CLK
10 nF
CLK_Out
R2
SerDes Refer.
CLK Receiver
R1
R1
100 Ω Differential PWB Trace
10 nF
Clock Driver
CLK_Out
R2
SD_REF_CLK
50 Ω
Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with the MPC8548E SerDes reference clock
input’s DC requirement.
Single-Ended CLK
Driver Chip
MPC8548E
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
SD_REF_CLK
33 Ω
Clock Driver
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω Differential PWB Trace
SD_REF_CLK
50 Ω
50 Ω
Figure 46. Single-Ended Connection (Reference Only)
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
67
FREESCALE [ Freescale ]
