PCI Express
Table 52. Differential Transmitter (TX) Output Specifications (continued)
Symbol
Parameter
Min
Nom
Max
Unit
Comments
T
Crosslink
random timeout
0
—
1
ms This random timeout helps resolve conflicts in
crosslink configuration by eventually resulting in
only one downstream and one upstream port.
See Note 7.
crosslink
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 50 and measured over
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 48.)
3. A T
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
= 0.30 UI for the
TX-EYE
TX-JITTER-MAX
transmitter collected over any 250 consecutive TX UIs. The T
median is less than half of the total
TX-EYE-MEDIAN-to-MAX-JITTER
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and
D– line (that is, as measured by a vector network analyzer with 50-Ω probes—see Figure 50). Note that the series capacitors
C
is optional for the return loss measurement.
TX
5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 50 for both V
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a.
and V
.
TX-D–
TX-D+
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a.
8. MPC8548E SerDes transmitter does not have CTX built in. An external AC coupling capacitor is required.
16.4.2 Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 48 is specified using the passive compliance/test measurement load (see
Figure 50) in place of any real PCI Express interconnect +RX component.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level
of the de-emphasized bit will always be relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the
TX UI.
NOTE
It is recommended that the recovered TX UI is calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (for example, least squares and median deviation fits).
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
72
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FREESCALE [ Freescale ]
