High-Speed Serial Interfaces (HSSI)
SD_TX or
SD_RX
A Volts
V
= (A + B)/2
cm
SD_TX or
SD_RX
B Volts
Differential Swing, V or V = A – B
ID
OD
Differential Peak Voltage, V
= |A – B|
DIFFp
Differential Peak-Peak Voltage, V
= 2*V
(not shown)
DIFFpp
DIFFp
Figure 38. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (current mode logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or
TD) is 500 mVp-p, which is referred as the single-ended swing for each signal. In this example, since the
differential signaling environment is fully symmetrical, the transmitter output’s differential swing (V
)
OD
has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between
500 and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other phase. The peak
OD
differential voltage (V
) is 500 mV. The peak-to-peak differential voltage (V
) is 1000 mVp-p.
DIFFp
DIFFp-p
15.2 SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and
SD_REF_CLK for PCI Express and serial RapidIO.
The following sections describe the SerDes reference clock requirements and some application
information.
15.2.1 SerDes Reference Clock Receiver Characteristics
Figure 39 shows a receiver reference diagram of the SerDes reference clocks.
•
•
The supply voltage requirements for XV
are specified in Table 1 and Table 2.
DD_SRDS2
SerDes Reference clock receiver reference circuit structure:
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown
in Figure 39. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω
termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
differential mode and single-ended mode description below for further detailed requirements.
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
62
Freescale Semiconductor
FREESCALE [ Freescale ]
