Enhanced Three-Speed Ethernet (eTSEC)
A timing diagram for TBI receive appears in Figure 16.
.
t
t
TRRX
TRRR
RX_CLK
t
t
TRRF
TRRH
Valid Data
RCG[9:0]
t
t
TRRDXKH
TRRDVKH
Figure 16. TBI Single-Clock Mode Receive AC Timing Diagram
8.2.6
RGMII and RTBI AC Timing Specifications
Table 33 presents the RGMII and RTBI AC timing specifications.
Table 33. RGMII and RTBI AC Timing Specifications
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
5
6
6
Data to clock output skew (at transmitter)
t
–500
1.0
7.2
45
0
—
8.0
50
—
—
500
ps
ns
ns
%
SKRGT
2
Data to clock input skew (at receiver)
t
2.8
8.8
SKRGT
5
3
Clock period
t
RGT
3, 4
5
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
Fall time (20%–80%)
t
/t
55
RGTH RGT
5
t
—
0.75
0.75
ns
ns
RGTR
5
t
—
RGTF
Notes:
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII and
RTBI timing. For example, the subscript of t represents the TBI (T) receive (RX) clock. Note also that the notation for rise
RGT
(R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is
skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3. For 10 and 100 Mbps, t
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
RGT
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t
of the lowest speed transitioned
RGT
between.
5. Guaranteed by characterization.
6. In rev 1.0 silicon, due to errata, t
document.
is -650 ps (min) and 650 ps (max). Please refer to “eTSEC 10” in the device errata
SKRGT
MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
36
FREESCALE [ Freescale ]
