Serial RapidIO
Table 68. Long Run Transmitter AC Timing Specifications—2.5 GBaud
Range
Characteristic
Symbol
Unit
Notes
Min
–0.40
Max
2.30
Output Voltage,
V
V
Volts
Voltage relative to COMMON of
either signal comprising a
differential pair
O
Differential Output Voltage
Deterministic Jitter
Total Jitter
800
1600
0.17
0.35
1000
mV p-p
UI p-p
UI p-p
ps
—
—
—
DIFFPP
J
J
—
—
—
D
T
Multiple output skew
S
Skew at the transmitter output
between lanes of a multilane
link
MO
Unit Interval
UI
400
400
ps
+/- 100 ppm
Table 69. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Range
Characteristic
Symbol
Unit
Notes
Min
–0.40
Max
2.30
Output Voltage,
V
V
Volts
Voltage relative to COMMON of
either signal comprising a
differential pair
O
Differential Output Voltage
Deterministic Jitter
Total Jitter
800
1600
0.17
0.35
1000
mV p-p
UI p-p
UI p-p
ps
—
—
—
DIFFPP
J
J
—
—
—
D
T
Multiple output skew
S
Skew at the transmitter output
between lanes of a multilane
link
MO
Unit Interval
UI
320
320
ps
+/- 100 ppm
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the
transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown
in Figure 58 with the parameters specified in Figure 70 when measured at the output pins of the device and
the device is driving a 100 Ω +/–5% differential resistive load. The output eye pattern of an LP-Serial
transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need
only comply with the Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
94
Freescale Semiconductor
FREESCALE [ Freescale ]
