Serial RapidIO
To ensure interoperability between drivers and receivers of different vendors and technologies, AC
coupling at the receiver input must be used.
17.1 DC Requirements for Serial RapidIO SD1_REF_CLK and
SD1_REF_CLK
For more information, see Section 15.2, “SerDes Reference Clocks.”
17.2 AC Requirements for Serial RapidIO SD1_REF_CLK and
SD1_REF_CLK
Figure 63lists the AC requirements.
Table 63. SDn_REF_CLK and SDn_REF_CLK AC Requirements
Symbol
Parameter Description
REFCLK cycle time
Min Typical Max Units
Comments
t
—
—
10(8)
—
—
ns
ps
8 ns applies only to serial RapidIO
with 125-MHz reference clock
REF
t
REFCLK cycle-to-cycle jitter. Difference in
the period of any two adjacent REFCLK
cycles
80
—
REFCJ
t
Phase jitter. Deviation in edge location with
respect to mean edge location
–40
—
40
ps
—
REFPJ
17.3 Equalization
With the use of high speed serial links, the interconnect media causes degradation of the signal at the
receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss
can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.
To negate a portion of these effects, equalization can be used. The most common equalization techniques
that can be used are as follows:
•
A passive high pass filter network placed at the receiver. This is often referred to as passive
equalization.
•
The use of active circuits in the receiver. This is often referred to as adaptive equalization.
17.4 Explanatory Note on Transmitter and Receiver Specifications
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at
three baud rates (a total of six cases) are described.
The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified
in Clause 47 of IEEE 802.3ae-2002.
XAUI has similar application goals to serial RapidIO, as described in Section 8.1. The goal of this standard
is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for
applications at the baud intervals and reaches described herein.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
91
FREESCALE [ Freescale ]
