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MPC8572ELVTAULD 参数 Datasheet PDF下载

MPC8572ELVTAULD图片预览
型号: MPC8572ELVTAULD
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: PC
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ Freescale ]
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Serial RapidIO  
17.7 Receiver Eye Diagrams  
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the  
corresponding Bit Error Rate specification (Table 71,Table 72, and Table 73) when the eye pattern of the  
receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver  
Input Compliance Mask shown in Figure 60 with the parameters specified in Table 74. The eye pattern of  
the receiver test signal is measured at the input pins of the receiving device with the device replaced with  
a 100-Ω +/– 5% differential resistive load.  
V
max  
DIFF  
V
min  
DIFF  
0
-V  
-V  
min  
DIFF  
DIFF  
max  
0
1
A
B
1-B  
1-A  
Time (UI)  
Figure 60. Receiver Input Compliance Mask  
Table 74. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter  
Receiver Type  
1.25 GBaud  
V
min (mV) V  
max (mV)  
DIFF  
A (UI)  
B (UI)  
DIFF  
100  
100  
100  
800  
800  
800  
0.275  
0.275  
0.275  
0.400  
0.400  
0.400  
2.5 GBaud  
3.125 GBaud  
17.8 Measurement and Test Requirements  
Because the LP-Serial electrical specification are guided by the XAUI electrical interface specified in  
Clause 47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided  
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4  
98  
Freescale Semiconductor  
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