Serial RapidIO
Table 73. Receiver AC Timing Specifications—3.125 GBaud
Range
Characteristic
Symbol
Unit
Notes
Min
Max
1600
Differential Input Voltage
V
200
mV p-p
UI p-p
UI p-p
Measured at receiver
Measured at receiver
Measured at receiver
IN
Deterministic Jitter Tolerance
J
J
0.37
0.55
—
—
D
Combined Deterministic and Random
Jitter Tolerance
DR
1
Total Jitter Tolerance
J
0.65
—
UI p-p
ns
Measured at receiver
T
Multiple Input Skew
S
—
—
22
10
Skew at the receiver input
between lanes of a multilane
link
MI
-12
Bit Error Rate
Unit Interval
Note:
BER
UI
—
ps
—
320
320
+/- 100 ppm
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 59. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
8.5 UI p-p
Sinusoidal
Jitter
Amplitude
0.10 UI p-p
22.1 kHz
Frequency
1.875 MHz
20 MHz
Figure 59. Single Frequency Sinusoidal Jitter Limits
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
97
FREESCALE [ Freescale ]
