Overview
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
— Interrupt summary registers allow fast identification of interrupt source
2
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I C controller
— Two-wire interface
— Multiple master support
2
— Master or slave I C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
2
— Optionally loads configuration data from serial ROM at reset via the I C interface
— Can be used to initialize configuration registers and/or memory
2
— Supports extended I C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
10/100 fast Ethernet controller (FEC)
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— Operates at 10 to 100 megabits per second (Mbps) as a device debug and maintenance port
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit)
Two three-speed (10/100/1Gb) Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers
— Support for different Ethernet physical interfaces:
– 10/100/1Gb Mbps IEEE 802.3 GMII
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– 10/100 Mbps IEEE 802.3 MII
– 10 Mbps IEEE 802.3 MII
– 1000 Mbps IEEE 802.3z TBI
– 10/100/1Gb Mbps RGMII/RTBI
— Full- and half-duplex support
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
5
FREESCALE [ Freescale ]
