Overview
1 Overview
The following section provides a high-level overview of the MPC8540 features.
shows the major
functional units within the MPC8540.
DDR
SDRAM
ROM,
SDRAM,
GPIO
IRQs
DDR SDRAM Controller
256KB
L2-Cache/
SRAM
e500
Coherency
Module
e500 Core
32 KB L1
I Cache
32 KB L1
D Cache
Local Bus Controller
Programmable
Interrupt Controller
Core Complex Bus
RapidIO Controller
OCeaN
MII
10/100
ENET
PCI/PCI-X Controller
4ch DMA Controller
Serial
DUART
TSEC
I
2
C
I
2
C
Controller
10/100/1G
RapidIO-8
16 Gb/s
PCI-X 64b
133 MHz
MII, GMII,TBI,
RTBI, RGMII
TSEC
10/100/1G
MII, GMII,TBI,
RTBI, RGMII
Figure 1. MPC8540 Block Diagram
1.1 Key Features
The following lists an overview of the MPC8540 feature set.
• High-performance, 32-bit Book E–enhanced core that implements the Power Architecture
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis. Separate locking for instructions and data
— Memory management unit (MMU) especially designed for embedded applications
— Enhanced hardware and software debug support
— Performance monitor facility (similar to but different from the MPC8540 performance monitor
described in Chapter 18, “Performance Monitor.”
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
2
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
