MPC8540CPX667JC 参数 Datasheet PDF下载

Clock Timing

4 Clock Timing

4.1 System Clock Timing

provides the system clock (SYSCLK) AC timing specifications for the MPC8540.

Table 7. SYSCLK AC Timing Specifications

Parameter/Condition

SYSCLK frequency

SYSCLK cycle time

SYSCLK rise and fall time

SYSCLK duty cycle

SYSCLK jitter

Symbol

f

SYSCLK

t

SYSCLK

t

KH

, t

KL

t

KHKL

/t

SYSCLK

—

Min

—

6.0

0.6

40

—

Typical

—

—

1.0

—

—

Max

166

—

1.2

60

+/- 150

Unit

MHz

ns

ns

%

ps

2

3

4, 5

Notes

1

Notes:

1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK

frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to

and

for ratio

settings.

2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. For spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 kHz of modulation

regardless of the input frequency.

4.2 TSEC Gigabit Reference Clock Timing

provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the

MPC8540.

Table 8. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition

EC_GTX_CLK125 frequency

EC_GTX_CLK125 cycle time

EC_GTX_CLK125 rise and fall time

LV

DD

=2.5

LV

DD

=3.3

EC_GTX_CLK125 duty cycle

GMII, TBI

RGMII, RTBI

t

G125H

/t

G125

45

47

—

55

53

Symbol

f

G125

t

G125

t

G125R

, t

G125F

Min

—

—

—

Typical

125

8

—

0.75

1

%

1,3

Max

—

—

Unit

MHz

ns

ns

2

Notes

Notes:

1. Timing is guaranteed by design and characterization.

2. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for LV

DD

=2.5V, and from 0.6 and 2.7V for

LV

DD

=3.3V.

3. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation EC_GTX_CLK125 duty cycle

can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.

MPC8540 Integrated Processor Hardware Specifications, Rev. 4

14

Freescale Semiconductor