Ethernet: Three-Speed Ethernet, MII Management
Table 27. MII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDD/OVDD of 3.3 V 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
TX_CLK data clock rise (20%–80%)
TX_CLK data clock fall (80%–20%)
Note:
tMTXR
tMTXF
1.0
1.0
—
—
4.0
4.0
ns
ns
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing
(MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference
symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of tMTX
represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
Figure 11 shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXF
tMTXH
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 11. MII Transmit AC Timing Diagram
8.2.2.2
MII Receive AC Timing Specifications
Table 28 provides the MII receive AC timing specifications.
Table 28. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
tMRX
—
—
400
40
—
—
—
65
—
—
ns
ns
%
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
MRXH/tMRX
tMRDVKH
tMRDXKH
35
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
10.0
10.0
—
ns
ns
—
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
27
FREESCALE [ Freescale ]
