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MPC8347ECVVAGDB 参数 Datasheet PDF下载

MPC8347ECVVAGDB图片预览
型号: MPC8347ECVVAGDB
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内容描述: MPC8347EA的PowerQUICC II Pro整合型主机处理器的硬件规格 [MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 99 页 / 727 K
品牌: FREESCALE [ Freescale ]
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Ethernet: Three-Speed Ethernet, MII Management  
Table 30. TBI Receive AC Timing Specifications (continued)  
At recommended operating conditions with LVDD/OVDD of 3.3 V 10%.  
Parameter/Condition  
Symbol1  
Min  
Typ  
Max  
Unit  
RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising  
PMA_RX_CLK  
2.5  
ns  
2
tTRDVKH  
2
RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising  
PMA_RX_CLK  
tTRDXKH  
1.5  
ns  
RX_CLK clock rise time (20%–80%)  
RX_CLK clock fall time (80%–20%)  
Notes:  
tTRXR  
tTRXF  
0.7  
0.7  
2.4  
2.4  
ns  
ns  
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs  
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing  
(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to  
the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals  
(D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. In general, the clock reference symbol  
is based on three letters representing the clock of a particular function. For example, the subscript of tTRX represents the TBI  
(T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For  
symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX).  
2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times  
of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0.  
Figure 15 shows the TBI receive AC timing diagram.  
tTRXR  
tTRX  
PMA_RX_CLK1  
RCG[9:0]  
tTRXH  
tTRXF  
Even RCG  
Odd RCG  
tTRDVKH  
tSKTRX  
tTRDXKH  
PMA_RX_CLK0  
tTRXH  
tTRDXKH  
tTRDVKH  
Figure 15. TBI Receive AC Timing Diagram  
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12  
Freescale Semiconductor  
30  
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